1. Field of the Invention
The present invention relates to new dynamic logic elements which are more compact than prior art elements and which have substantially more drive capability for charging up successive output stages.
2. Description of the Prior Art
The basic prior art logic element is an inverter having a switching (driver) transistor and a pullup (load) device which is either a passive resistor or diode, or an active transistor which in a dynamic circuit is periodically clocked to conserve power. A typical prior art structure of this type is disclosed, for example, in U.S. Pat. Nos. 3,471,712 and 3,668,424. In the '712 patent, a logic circuit is disclosed employing a pair of field effect transistors each of which is connected in series with a non-linear constant voltage load element. Other similar logic structures are disclosed in U.S. Pat. No. 3,395,291 issued July 30, 1968 on an application of Bogert and U.S. Pat. No. 3,393,325 issued July 19, 1968 on an application of Borror et al.
Dynamic (multiphase) logic is a well established concept, both in logic applications and in serial (shift register) type memory applications. A good description of dynamic MOS inverters and gates is given in the book "IC in Digital Electronics" (Barna and Porat, 1973). Related prior art U.S. patents are U.S. Pat. Nos. 4,107,548 by Sakaba et al. (Ratioless Type MIS Logic Circuit), 3,702,945 by Faith et al (MOS Circuit with Nodal Capacitor Predischarge Means), 4,040,015 by Fukuda et al. (Complementary MOS Logic Circuit), 4,017,741 by Briggs et al. (Dynamic Shift Register Cell), 3,651,334 by Thompson (Two Phase Ratioless Logic Circuit with Delayless Output), 3,838,293 by Shah (Three Clock Phase, Four Transistor Per Stage Shift Register), and 3,601,627 by Booher (Multiple phase logic gates for shift register stages) showing a four phase shift register (FIG. 4).
The basic four phase ratioless prior art shift register is shown in FIG. 1. Transistor 102 is the load device, transistor 101 is the switching device, and transistor 103 is the transfer device. When .phi..sub.1 is taken high with .phi..sub.2 low (for an NMOS implementation) capacitor C.sub.1 (104) is charged high. If V.sub.in is high, C.sub.1 is discharged to ground when .phi.`is brought low and .phi..sub.2 is pulsed high. If V.sub.in is low C.sub.1 remains charged high for a period of time measured in several milliseconds at room temperature. Normally node 106 is at ground potential, but in some implementations it is connected to the .phi..sub.1 clock so that no DC power is dissipated when .phi..sub.1 is brought high. All prior art dynamic logic devices share a common substrate which is normally tied to ground or to a negative potential (VBB) for NMOS implementation.
The structure shown in FIG. 1 represents a full stage of a shift register. To operate properly as a shift register, two half stages are required, each having their own two clock phases, with .phi..sub.3, .phi..sub.4 of the second half stage corresponding to clock phases .phi..sub.1, .phi..sub.2 of the first half stage. A full clock cycle consists of .phi..sub.1 +.phi..sub.2 +.phi..sub.3 +.phi..sub.4.
Each of the above structures uses a loading element separate from the logic elements. Accordingly, the densities of these structures are inherently limited by the minimum number of components required in the logic. Thus, regardless of cell size, the minimum packing density is equal to the number of devices in a chip times the size of each device.